(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit compensating variations of delay time and, more particularly, to a technique for compensating variations of delay time cause by an input signal pattern.
(b) Description of the Related Art
In a semiconductor device, the circuit specification is generally limited by a delay time for signal processing. Especially, the circuit specification is limited by a largest delay time among the delay times for signal processing based on a variety of input signal patterns.
Referring to FIG. 1, a conventional semiconductor integrated circuit includes an internal circuit 101, input flip-flops 103, and a source potential reduction circuit 102, wherein the input flip-flops 103 receive input data IN1, which have various signal patterns, through input signal lines 104 to deliver the input data to the internal circuit 101. The internal circuit 101 acts as a functional circuit, which operates therein for processing the input data IN1 to deliver output data through the output signal lines 105 after the processing. The internal circuit 101 may be called a functional circuit.
The power source potential Vint is supplied to the internal circuit 101 from the source potential reduction circuit 102 which generates a reduced potential for the source potential Vint and delivers the same through an internal source line 106 for achieving alleviation of the electric field and reduction of the power dissipation in the internal circuit 10. The reduced source potential Vint allows reduction of the dimensions of the semiconductor elements in the internal circuit 101, whereby the semiconductor integrated circuit has a lower power dissipation and a reduced occupied area thereof as well as a higher operational reliability of the internal circuit 101.
In general, a higher internal source potential allows a higher operational speed in an LSI (large-scaled integrated circuit). In the case of the internal circuit 101 being implemented by a static circuit having CMOS transistors, the power dissipation of the internal circuit is expressed by C Vintxc3x97Vint/2 wherein C is the sum of the load capacitances of the internal circuit. Thus, by reducing the internal source potential Vin, the power dissipation can be effectively reduced irrespective of some power dissipation caused in the source potential reduction circuit 102. The source potential reduction circuit 102 may be provided outside the chip of the semiconductor integrated circuit as a power IC (integrated circuit) or a DCxe2x80x94DC (direct current-direct current) converter.
The internal circuit 101 outputs the results of the processing therein based on input signal patterns, and the delay of the internal circuit 101 or the operational speed thereof depends on the input signal patterns IN1 received therein.
For example, if the input data IN1 are address signals for a semiconductor memory device such as shown in FIG. 2, the input signal patterns IN1 specify the locations of the memory cells accessed by the input signal patterns in the chip of the memory device. In this case, the read time for the memory cells depends on the distance of the signal path between the input/output section 111 and the accessed memory cells.
More specifically, the semiconductor memory device of FIG. 2 includes a plurality of memory banks 114 to 121, each of which includes a plurality of memory cells arranged in a matrix. Each of the memory cells is connected to a bus line such as 132 and 134 via an in-bank line such as 133 and 135. The bus lines 132 and 134 are connected to an ECC (error correcting code) section 112 directly or via signal line 131, which pass through a control circuit section (CCS) 113.
The ECC section 112 is connected to an input/output (I/O) section 111, which functions as interface with external circuits.
The I/O lines 136 corresponds to both the input signal line 104 and the output signal line 105 in FIG. 1, and the flip-flops 103 correspond to a part of the I/O section 111. The potential reduction circuit 112 corresponds to a part of the control circuit section 113, and the rest of the constituent elements in FIG. 1 is included in the internal circuit 101.
In operation, the address signal supplied through the I/O section 111 passes the ECC section 112, and is decoded in the control circuit section 113. More specifically, the most significant three bits of the address signals specify one of the eight memory banks 114 to 121, and the next significant fourth bit specifies one of the pair of half sections in each memory bank. The remaining less significant bits specify the address of the desired memory cells in each half section in each memory bank by using a row decoder and a column decoder. The read data from the specified memory cells include redundancy data for an error correction as well as the data stored in the specified memory cells.
The read data are transferred from the in-bank signal lines 133 or 135, via the bus lines 132 or 134 after amplification thereof, to the ECC section 112. The read data from the far memory banks 118 to 121 are transferred additionally via signal lines 131 which pass through the control circuit section 113. The ECC section 112 operates for an error correction processing based on the redundancy data, and outputs the read data to the I/O section 111 after the error correction. The I/O section 111 delivers the read data outside the memory device via the I/O lines 136.
The travel distance both for input address signals to reach selected memory cells and for the read data to be output depends on the input address patterns, whereby the access time with selected memory cells follows the exemplified graph shown in FIG. 3. Each of the input addresses shown therein includes most significant four bits which specify the memory bank as well as the half section thereof and the other less significant bits which specify the memory cell therein. Abrupt changes in the graph are due to the difference in the path length between the half section of the memory bank and the I/O section 111, whereas the gradual (upward) change between the adjacent abrupt changes is due to the difference in path length between the memory cells in each half section of each memory bank.
The dependency of the access time on the input address pattern shown in FIG. 3 follows the configuration of the memory banks 114 to 121, location or arrangement of the I/O section 111, the material or structure of the signal lines such as 131, electric characteristics of the transistors for driving the signal lines etc. The variation of the delay time depending on the input signal pattern is inevitable because all the memory cells cannot be located at a single position. Thus, the maximum delay time tmax, as shown in FIG. 3, is considered to represent the performance of the overall circuit.
The variations of the delay time due to the input signal patterns also result from, in addition to the different path lengths, a different speed at which each instruction is executed by such circuits as CPU (central processing unit), MPU (micro processing unit), DSP (digital signal processor) or so on which interprets a variety of commands and executes the interpreted command in case by case. In the processor, such simple instructions as logical operation coexist with such complicated instructions as multiplication. This fact causes large difference of delay times depending on input commands. In specification, delay time of each command is raised to agree with onexe2x80x94several fold clock cycles, therefore a fractional difference of delay time remains to be compensated by this invention.
xe2x80x9cIEEE JOURNAL OF SOLID-STATE CIRCUITSxe2x80x9d, VOL. 25, October, 1990, pp1136-1140 describes a compensating circuit for compensating the variations of the delay time by using a phase locked loop. FIG. 4 shows the described compensating circuit used for an internal circuit 141. The compensating circuit with phase locked loop includes a voltage controlled oscillator (VCO) 142, a frequency divider 143, a phase comparator 144, a charge pump 145 and a low-pass filter 146.
The low-pass filter 146 of the compensating circuit supplies an internal source potential Vint to the internal circuit 141 and the VCO 142, which outputs a frequency based on the internal source potential Vint. The frequency divider 143 divides the output frequency of the VCO 142 into 1/N, and the comparator 144 compares an output from the frequency divider 143 with the external clock signal CLK. The comparator 144 delivers an UP signal if the clock signal CLK leads in phase with respect to the output from the frequency divider 143 and delivers a DOWN signal if the clock signal CLK lags in phase with respect to the output from the frequency divider 143. The charge pump 145 raises the output current thereof to the low-pass filter 146 upon receiving the UP signal, thereby raising the internal source potential Vint. The charge pump 145 lowers the output current thereof to the low-pass filter 146 upon receiving the DOWN signal thereby lowering the internal source potential Vint. The low-pass filter 146 suppresses the fluctuation of the internal source potential Vint.
Thus, the internal source potential Vint is controlled so that the output frequency from the VCO 142 assumes 1/N of the frequency of the external clock signal CLK. In this scheme, if the semiconductor integrated circuit is designed so that the change of the delay time of the internal circuit 141 under being supplied with the internal source potential Vint corresponds to the change of the output frequency of the VCO 142 against the variations caused by the fabrication process, change of the operational temperature and the fluctuations of the external power source potential Vdd, the relationship between the delay time of the internal circuit 141 and the clock cycle of the clock signal CLK is free from the influence by these variations.
FIG. 5 shows the improved access time obtained in the internal circuit 141 shown in FIG. 4, plotted by solid line, and compared to the access time in the conventional circuit of FIG. 1 which is plotted by dotted line. The dotted line shows, in addition to the variations caused by the input signal pattern, variations of the delay time caused by variations of fabrication process, operational temperature and external source potential Vdd.
On the other hand, in the described circuit of FIG. 4, the delay time of the respective elements in the VCO 142 and the delay time of the respective elements in the internal circuit 141 change similarly to one another upon variations of fabrication process, operational temperature and external source potential Vdd. Thus, the control of the internal source potential Vint allows the access time to be reduced from the dotted line to the solid line, and the overall performance of the internal circuit can be expressed by the maximum reduced delay time txe2x80x2max.
In the described circuit, however, the variations of the access time caused by the input signal patterns remain similarly to the conventional circuit. The technique for compensating the variations of the delay time is also described in Patent Publications JP-A-8-223018, -7-264056, and -9-139656, which involve similar problems however.
As described above, first, the conventional integrated circuit has variations of the delay time caused by the input signal pattern, and the performance of the integrated circuit is limited by a few of the possible signal patterns. Since the chip size of the integrated circuit becomes larger and the variations of the delay time oftener limit the performance of the integrated circuit along with the higher-speed operation thereof, the dependency of the delay time on the input signal pattern will become larger.
Second, reduction of the power dissipation is not satisfactory because the internal source potential Vint of the internal circuit is adjusted at a relatively higher potential for adapting the specific input patterns, such as xe2x80x9c1001XXXXxe2x80x9d and xe2x80x9c1111XXXXxe2x80x9d shown in FIG. 5, which provide larger delay times for the read time.
Third, improvement of the reliability of the semiconductor integrated circuit is limited due to the reason specified above in connection with the limited reduction of the power dissipation, because higher voltage applied to elements constituting the circuits lead to lower reliability.
In view of the above, it is an object of the present invention to provide a semiconductor integrated circuit capable of compensating variations of delay time for signal processing to obtain a reasonable specification for the semiconductor device without degrading a high reliability thereof.
In one aspect of the present invention, the present invention provides a semiconductor integrated circuit including an input section for receiving an input signal pattern, an internal circuit for operating based on the input signal pattern for a specific function, a pattern examination block for examining the input signal pattern to estimate a delay time in the internal circuit and deliver a delay control signal based on the estimated delay time, and a delay control block for controlling the delay time of at least a part of the internal circuit based on the delay control signal.
In accordance with the semiconductor integrated circuit of the present invention, the control of the delay time in the internal circuit based on the delay control signal can reduce variations of the delay time in the output of the internal circuit caused by the input signal pattern
The control of the delay time can be obtained by controlling the internal source potential of the at least a part of the internal circuit, controlling the back bias voltage of the transistors in the at least a part of the internal circuit, as described in xe2x80x9cSubstrate Noise Influence on Circuit Performance in Variable Threshold-Voltage Schemexe2x80x9d in the xe2x80x9cProceedings of the International Symposium on Low Power Electronics and Design 1996xe2x80x9d, pp.309-312, or controlling both the internal source potential and the back bias voltage, as described in xe2x80x9cElastic-Vt CMOS Circuits for Multiple On-Chip Power Controlxe2x80x9d in the xe2x80x9cSolid-State Circuits Conferencexe2x80x9d, pp.300-301.
Both the descriptions in the publications for controlling the internal source voltage and/or the back bias voltage are incorporated in this text by reference.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.